Design of fiber channel interface control chip for

  • Detail

In order to meet the requirements of storage network and Next Generation Avionics System for fiber channel network, a new design scheme of fiber channel network interface control chip is proposed. The RTL design of the interface control chip is realized with Verilog, and the function simulation and verification are completed. The control software design of the interface control chip is completed through embedded PowerPC. Taking virtex II Pro Series FPGA of Xilinx company as the platform, the interface control chip prototype is realized

keywords fibre channel FPGA interface control chip embedded PowerPC


as the product of the combination of channel technology and network technology, fibre channel is an open network with high real-time, high reliability, high bandwidth and high cost performance. Any equipment that needs to be connected to the fibre channel network needs the corresponding network interface card (NAC), and the core of the network interface card is the interface control chip. At present, according to the difference of the maximum experimental force (loading capacity) that it can test, the load sensor is also divided into 50N and 5kn, and different types of fiber channel interface control chips in the market are few and expensive, and the core technology is mastered, but the so-called imports should be all foreign companies imported from abroad; The military fibre channel interface control chip is simply not available in the market for well-known reasons. Therefore, designing a fiber channel network interface control chip with independent intellectual property rights according to the fiber channel standard is of great significance to the economic and military development of our country

because the fibre channel standard is a cluster of very large and complex protocols, different characteristics are suitable for different application environments; Because the fibre channel standard is still in the development stage and the content of the standard is still changing, it is a very suitable choice to choose FPGA as the carrier of the current interface control chip. On the one hand, for different application environments, the corresponding functional modules can be appropriately reduced, which can not only meet the application needs, but also reduce the cost; On the other hand, for the changes of the protocol, the implementation based on FPGA can easily update the old version design

1 protocol analysis

similar to the OSI reference model, the fibre channel protocol cluster also organizes each protocol in a hierarchical manner. Its hierarchical model is shown in Figure 1

as a data transmission protocol, fibre channel supports many upper layer protocols, including via, SCSI, IPv4, IPv6, sbccs, ASM, etc. Before transmitting data for these protocols, it is necessary to map the data to be sent into the specified format, and the FC-4 layer implements this mapping. For each supported upper layer protocol, there is a mapping protocol corresponding to it

The fc-3 layer is a general service layer, which provides a series of general services for the mapping layer protocol. Several important services include exchange registration, port registration and logout services

fc-2 layer is the most important layer in the fibre channel protocol. It defines the rules and mechanisms for end-to-end transmission of data blocks, including different types of services, frame format definitions, sequence fragmentation and reassembly, switching management, address allocation and multicast management

fc-1 layer defines serial coding and decoding. For this specification, 8B/10B coding is specified

fc-0 layer is the physical layer specification of fibre channel protocol, which defines the transmitter, receiver, transmission medium and the interface specification between them. The transmission rate is also defined here

2design scheme

through the analysis of the protocol, it is concluded that the mapping layer protocol is closely related to the specific application environment and should be implemented by the user himself. The interface control chip can be logically divided into three parts: general service module, end-to-end IU transmission and buffer to buffer frame transmission; In terms of implementation, it can be divided into software part and hardware part. The system block diagram of interface control chip is shown in Figure 2

the PowerPC and memory controller on the left of Figure 2 are interconnected through PLB bus to build the operation platform of the software part of Linux operating system and interface control chip

powerpc architecture also includes a general OPB bus for the interconnection of external devices. The OPB bus is connected to the PLB bus through a plb-opb bridge, as shown on the right side of Figure 2. There is only one external device connected to the OPB bus, that is, the fibre channel transmission core

user interface defines the user interface of the interface control chip. According to different application environments, this module has different implementation methods, such as PCI or USB

when the user has data to send, the user interface of the interface control chip saves the data in the data memory inside the chip in the standard format, and requests the data transmission service of the interface control chip by setting the corresponding register. Then, the software code takes over the data and assigns corresponding software resources (exchange status block, sequence status block, etc.) for this data (IU) transmission to record the sending status of the data. After the corresponding processing is completed, PowerPC notifies the transmission check data for processing through the interface provided by the fibre channel transmission core, including slicing, framing, CRC calculation, 8B/10B coding and other tasks. Finally, the transmission core outputs high-speed serial data through the output pin to modulate the optical transmitter and send it to the optical fiber link

when receiving data from the input link, the transmission core first processes the data, including bit synchronization, serial parallel conversion, 8B/10B decoding, word synchronization, ordered set detection, CRC check and frame extraction. When the effective frames are received and stored in the receiving buffer, the hardware module sets the corresponding registers to notify the power PC, and then the power PC processes the received frames, including allocating the corresponding software resources and reloading the frames. When all frames belonging to a sequence are correctly received, PowerPC notifies the user module through the user interface module, and the user module processes the data by itself after receiving it

3 hardware design

the hardware part of the interface control chip, that is, the fibre channel transmission core in Figure 2, is responsible for transmitting data frames from the transmission buffer to the reception buffer at the other end of the link according to the standard format. In order to complete this task correctly and effectively, the hardware part of the interface control chip realizes the following functions: buffer to buffer flow control, link level error detection and recovery, word synchronization, ordered set detection, frame extraction, 8B/10B codec and serial parallel/parallel serial conversion. The functional block diagram of the hardware part of the interface control chip is shown in Figure 3

3.1 transmission control logic

the function of transmission control logic is to control the transmission sequence of frames, primitive signals and primitive sequences to make them conform to the fibre channel standard, mainly including ensuring that there is sufficient interval between consecutive frames and inserting primitive signals between frames

the CRC value of the transmitted frame is also calculated by the transmission control logic. The traditional serial calculation method cannot reach the required rate. Here, the parallel CRC algorithm is used for calculation, and each clock effective edge can calculate 32-bit data, which greatly improves the data throughput

buffer to buffer flow control is also implemented in the send control logic. The transmission control logic maintains a counter indicating the number of frames that have been sent but have not yet been confirmed. Each time 1 frame is sent, the counter is incremented by 1; When receiving R_ When RDY primitive signals, the counter decreases by 1. If this value is less than BB in the configuration register_ Credit value, it means that the frame can be sent continuously; Otherwise, it indicates that the target port has no available receive buffer, and the transmission control logic will not send out frames at this time

3.2 the data decoded by the receiving control logic

8b/10B is byte data, and all ordered sets are words, so it is necessary to correctly distinguish the word boundary in the input byte stream. The word synchronization module in the receiving control logic works together with the receiving state machine to realize this function. The receiver state transition diagram specified in the standard is shown in Figure 4

3.3 8B/10B encoding and decoding

traditional encoding and decoding methods are implemented by digital logic, mainly to save logic resources. Because FPGA contains abundant ram, as the carrier of encoding and decoding, it can reduce the complexity and improve the speed of encoding and decoding. The data to be encoded is input as the address line, and the encoded data is stored in RAM and output from the data line

3.4 port state machine

as the core of link level error detection and recovery, port state machine monitors the status of the transceiver link. Whenever the link state is abnormal, the port state machine will start different link recovery protocols to recover the link according to the cause of the abnormality. If the recovery fails, the port state machine will report to the upper layer through the status register. For layout considerations, the simplified state transition diagram of the port state machine is shown in Figure 5. The "t" beam and column will break under 7 tons load; With the help of wedge system, other modules are asynchronous FIFO: because the receiving part of the interface control chip uses the clock recovered from the received data, it is asynchronous with the master clock of the chip. When the received data is handed over to other modules working on the master clock for processing, rate adjustment is required. Asynchronous FIFO is used to realize this function. Serial parallel/parallel serial conversion: high-speed serial parallel conversion has high requirements for device performance. A dedicated hard core (rocketoio) is integrated in FPGA to realize this function, so it can be configured appropriately. This saves the special serial parallel conversion chip

the configuration register stores a series of working parameters, such as (r_t_tov, e_d_tov, etc.), and initializes the register with the default value after reset. After registration, update the register with the new value

the fibre channel transmission core indicates its current state (such as, offline, etc.) through the status register

4 software design

the software part of the interface control chip is responsible for parameter negotiation and processing transactions related to end-to-end data transmission, including port registration and exchange registration, providing different types of services, end-to-end flow control, sequence level error detection and recovery

in order to simplify the software design, the embedded Linux operating system is used as the software running environment of the interface control chip. By designing a series of operation functions, the whole software system is realized. The most important functions include port registration function, IU sending function and receiving frame processing function

4.1 port registration function plogin_ In()

registration includes port registration and exchange registration. The process of the two kinds of registration is similar. Here, only port registration is analyzed. After the system starts, the working parameters of the chip need to be configured, and the registration function selects the registration method according to the user's configuration. If the user specifies implicit registration, the registration function reads the default configuration parameters from the configuration file to configure the chip; If the user specifies explicit registration, the registration function sends a registration request. After the other port returns a response, the registration function configures parameters with the data of the response. The workflow of the port registration function is shown in Figure 6

4.2 IU sending function sen

4.3 receiving frame processing function FRM_ Rcved()

when the fibre channel transmission core receives and stores the correct frame in the receive buffer, it notifies PowerPC through the status interface. At this time FRM_ The rcved() function starts to process the frame header. There are many parameters to check in the frame header, which will not be repeated here. If there is no error in the parameters in the frame header, the function is this

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